In computer systems, improvements in the performance and efficiency of software enable new and improved applications and functionality. This synergistic interaction between more powerful software that requires more powerful hardware which in turn enables more powerful software has been the driver of the information revolution of the past several decades. In the history of “instruction set compatible” computing, newer generations of computer hardware have provided substantial improvements to existing applications while new and re-compiled applications provided additional improvements beyond the hardware ones.
As computer hardware architecture technology has matured, however, it has become increasingly difficult for microprocessor vendors to deliver increased performance through micro-architecture techniques. Because technology is reaching the limits of cost-effective techniques to improve the instruction-level parallelism within threads of computation, many in the industry view thread-level parallelism as the best technology with which to continue the performance treadmill. Accordingly, manufacturers have begun to produce “multi-core” CPUs that include multiple processors within a single semiconductor “chip.” In concert with this, the leading SW developers have begun to call for applications to be re-written to take advantage of the performance potential of multi-core processors.
As a consequence of these developments, existing applications often can no longer expect substantial improvements in performance with new generations of computer hardware. Large performance improvements are typically only available to re-written applications that are specifically targeted for newer multi-core processors. Moreover, the process of programming a multi-threaded application to take advantage of a multi-processor architecture is often complex and error-prone.